Digital systems design and verification becomes more difficult as the size of the system grows. To solve this problem, many CAD tools have been developed, including simulation. However, as systems increase in size and complexity, simulating the system becomes very costly, both in time and space. For most cases that use simulation, only a subset of the total possible simulation patterns is used for design verification. This paper describes a simulation tool which applies effective methodologies such as: error compression and sampling, for reducing simulation time and resources. These methods satisfy confidence level expectations for design verification using either reduced design errors or reduced test sets.
Keywords: Fault Simulation, Design Error Simulation, CAD, Sampling, Error Compression