| 8:45 | WELCOME |
| 8:45-9:15 | Bypass-Efficient Instruction Dispatch for Clustered Microarchitecture, Zhengming FU and Dan Friendly, Department of Computer Science, Yale University |
| 9:15-9:45 | Single Instruction Fetch Does Not Inhibit Instruction-Level Parallelism, Christian D. Freitas and Alberto F. De Souza, Departamento de Informatica, UFES, Brazil |
| 9:45-10:15 | Modeling Program traces with Nested Loops, Philippe Clauss, ICPS-LSIIT, Universite Louis Pasteur, France |
| 10:15-10:30 | BREAK |
| 10:30-11:00 | Flexible Instrumentation for Software Dynamic Translation, Naveen Kumar and Bruce Childers, Department of Computer Science, University of Pittsburgh |
| 11:00-11:30 | Analyzing the Limits of Trace Reuse in a Dynamic Conditional Execution Architecture, Tatiana G. S. Santos et al, Departamento de Informatica, UFRGS, Brazil |
| 11:30-12:00 | Characterizing Inter-Execution and Inter-Application Optimization Persistence, Kim Hazelwood and Michael Smith, Electrical Engineering and Computer Science, Harvard University |
| 12:00-12:30 | A Comparative Analysis Between EPIC Static Instruction Scheduling and DTSVLIW Dynamic Instruction Scheduling, Sandro C. Santana, Alberto F. De Souza and Peter Rounce, Departamento de Informatica, UFES, Brazil and Department of Computer Science, University College London |